This invention relates to programmable logic devices, and more particularly to programmable logic devices with increased logic and interconnection capability.
Programmable logic devices are well known as is shown, for example, by Pedersen et al. U.S. Pat. No. 5,260,610, Cliff et al. U.S. Pat. No. 5,260,611, Cliff et al. U.S. Pat. No. 5,689,195, and Cliff et al. U.S. Pat. No. 5,909,126. All of these references are hereby incorporated by reference herein in their entirety.
There is continued interest in programmable logic devices with greater logic capacity. This calls for devices with larger numbers of regions of programmable logic. It also call e for logic devices with more programmable interconnection resources for making needed connections between the increased numbers of logic regions. It is important, however, to add interconnection resources judiciously so that those resources do not begin to take up excessive amounts of space on the device, thereby unduly interfering with the amount of additional logic that can be included in the device. To accomplish this it would be desirable to find ways to organize programmable logic devices, and especially the interconnection resources in programmable logic devices, so that the efficiency of utilization of the interconnection resources can be greater. In this way more interconnectivity can be provided in the device to serve more logic in the device without simply directly scaling up the interconnection resources with the increased logic capability.
An example of a possible problem associated with merely scaling up known programmable logic device architectures is illustrated by the case of the architecture shown in above-mentioned Cliff et al. U.S. Pat. No. 5,689,195. In this type of device regions of programmable logic are disposed on the device in a plurality of rows of such regions. Each row has an associated plurality of horizontal interconnection conductors for selectively conveying signals to, from, and between the regions in that row. Region-feeding conductors are associated with each region for selectively bringing signals from the associated horizontal conductors into the region as input signals. Output signals produced by each region are selectively applied to the associated horizontal conductors. Vertical interconnection conductors are provided for selectively conveying signals between the rows of the device. Accordingly, a programmable logic device having this type of architecture basically comprises a row of logic regions and associated interconnection conductors that has been replicated a number of times and then provided with vertical interconnection conductors for interconnecting the rows. To meet the demand for larger and larger devices it may not be practical to indefinitely increase the number of regions in a row or the number of rows due to manufacturing constraints. For example, the aspect ratio of the device may tend to become too large.
In view of the foregoing, it is an object of this invention to provide improved organizations ("architectures") for programmable logic devices.
It is a more particular object of this invention to provide programmable logic device architectures that can efficiently accommodate larger numbers of programmable logic regions.
It is another more particular object of this invention to provide programmable logic device architectures which permit higher densities of logic regions and which have more uniform horizontal and vertical characteristics so that there is less preference for one direction over the other and therefore less tendency toward designs with high aspect ratios.